1. Field of the Invention
This invention relates to synchronizers for digital logic networks, computers and synchronous sequential networks and is in the general area as copending U.S. patent application Ser. No. 285,207 to Guttag, et al which is assigned to the assignee of the present invention.
2. Description of the Prior Art
Modern computers are synchronous in nature. That is, they include synchronous sequential networks that are regulated by clock pulses. This synchronous nature is a result of the ease of design and integration of smaller sequential circuits contained on integrated chips. However, to interface to the external world, the sequential networks must also interface with asynchronous inputs. A asynchronous signal is a signal that occurs at some time not subject to the regulation of the clock circuitry for the synchronous circuit. The requirement for an input to the synchronous network is the asynchronous signal be maintained so that the synchronous circuit can detect its presence. In previous computers this has been done with a flip flop. In other words, the asynchronous signal is an input to a flip flop which is clocked by the internal clock of the asynchronous system. The existence of the asynchronous input is then stored as a level output of the flip flop. After this input has been acknowledged, the flip flop is then cleared in order to receive additional asynchronous inputs. Problems with this circuit can occur when the flip flop is being cleared at the same time an asynchronous event occurs. In other words, as the circuit is being clocked, the asynchronous level is being raised. At the falling edge of the clock, the occurrence of an asynchronous signal can place the flip flop in what is termed a metastable condition. This is a condition in the flip flop where the flip flop is between a logic 0 and a logic 1. The logic 0 and the logic 1 states are representative of the output voltages of the flip flop. In the metastable state the voltage maintained by the flip flop is between the regions designated for logic 0 and logic 1. The probability of this type of condition occurring is directly related to the speed of the machine since the speed of the device determines the rate that the flip flop receives the clock signal and thus determines the number of clock falling edges present per unit time. As the speeds of synchronous devices increases, the occurrence of this asynchronous interface problems becomes more prelevant.
Many articles have been written about the asynchronous interface problem. The solution suggested include the use of synchronizers to synchronize the occurrence of the asynchronous event with the synchronous circuit clock. One such paper is "Beware the Synchronizer" by T. J. Chaney, F. M. Ornstein and W. M. Littlefield, COMPCON-72, IEEE Computer Society Conference, San Francisco, Calif., Sept. 12-14, 1972. This paper suggested the use of a flip flop with a metastable detector. In other words, a circuit that detects the existence of a metastable condition in the flip flop. Another solution suggested by G. Elineau and Warner Wieabeck in IEEE Transactions on Computers, Vol. C-26, No. 12, December 1977, p 1277-1279 includes a new type of JK flip flop for synchronizers. This flip flop is specifically developed for synchronizer circuits and allows the internal clock of the synchronizer circuit to operate at a higher speed. A third solution suggested by Leonard Marino in his paper, "The Effect of Asynchronous Inputs on Sequential Network Reliability", in IEEE Transactions on Computers, Vol. 26, No. 11, November 1977, p. 1082-1090 is the use of delays to allow the flip flops to settle to a stable state to prevent any so called runt pulses from generating metastable conditions. However, another paper by T. J. Chaney and C. E. Molner entitled, "Anomalous Behaviour of Synchronizer and Arbitrator Circuits", appearing in the IEEE Transactions on Computers, Vol. C-22, No. 4, April 1973, pp 421-422, states that use of delays will not completely solve the problem but only allow for some improvement. Therefore, the prior art allows certain solutions to improve the performance of synchronizers, but the goal of synchronizer reliability is still elusive. The goal for synchronous system designers is to design a synchronizer with reliability that is as great as the reliability of the component in the synchronous circuits.